/*****************************************************************************/
/**
*
* @file adau1761.h
*
* Header file for adau1761.c.
*
* <1> The addresses of registers are discontinuous, so it's inappropriate to
*     set all registers in continuous mode.
* <2> Pll registers should be writen in single continuous mode, from subaddress
*     0x4002 to 0x4007. And should not be read from or after 0x4003. For example,
*     if you want to get pll status value in register 0x4007, the user should
*     make a single continuous read from or before 0x4002.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver   Who    Date   	Changes
* ----- ---- ---------- -------------------------------------------------------
* 0.01  abu  05/31/2019 Created
* </pre>
*
*------------------------------------------------------------------------------
* Author: abu	E-mail:	abu_liu@aliyun.com
*				Blog:	https://blog.csdn.net/ClamerKorallen
*				Gitee:	https://gitee.com/abu_liu
*------------------------------------------------------------------------------
*
******************************************************************************/

#ifndef ADAU1761_H
#define ADAU1761_H

#ifdef __cplusplus
extern "C" {
#endif

/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_printf.h"
#include "xiicps.h"
#include "uiicps.h"
#include "debug.h"

/************************** Constant Definitions *****************************/
#define ADAU1761_CPU_IIC_PTR	(&uiic0ps)	//declare which iic device is being used by chip

/*************************** Hardware constants ******************************/
#define ADAU1761_CHIP_ADDR		0x3b	//A1/A0 are defined by PL
#define ADAU1761_SUBADDR_HIGH	0x40	//higher byte of base address
#define ADAU1761_SUBADDR_LOW	0x00	//lower byte of base address
#define ADAU1761_MCLKMHZ		24U		//Mclk is derived from PL
#define ADAU1761_REG_NUM		0xFB	//number of registers
#define ADAU1761_IIC_CLK		384600U	//iic clock rate, in Hz
#define ADAU1761_SUBADDR_BYTENUM	2U	//subaddress  bytecnt

#define	ADAU1761_PLL_REGADDR	0x02	//read-only purpose, donot write to
										//	this register in single byte.
//----------------------------------------------------------------------------
// sets about clock control, select 3 of 8 macros in 3 groups, AND them, then
// write the value to this register
#define	ADAU1761_CLKCTL_REGADDR		0x00	//clock control register address

#define ADAU1761_CLKSRC_PLL_MASK	0x08	//pll selected as clock source
#define ADAU1761_CLKSRC_MCLK_MASK	0x00	//mclk selected as clock source

#define ADAU1761_CLKFRE_256FS_MASK	0x00	//clock frequence 256xFs mask
#define ADAU1761_CLKFRE_512FS_MASK	0x02	//clock frequence 512xFs mask
#define ADAU1761_CLKFRE_768FS_MASK	0x04	//clock frequence 768xFs mask
#define ADAU1761_CLKFRE_1024FS_MASK	0x06	//clock frequence 1024xFs mask

#define ADAU1761_CORECLK_EN_MASK	0x01	//core clock enable mask
#define ADAU1761_CORECLK_DIS_MASK	0x00	//core clock disable mask
//----------------------------------------------------------------------------

//----------------------------------------------------------------------------

#define ADAU1761_REC_MIXER_LEFT_CTL_0_ADDR		0x0A	//rec mixer left 0
#define ADAU1761_REC_MIXER_LEFT_CTL_1_ADDR		0x0B	//rec mixer left 1
#define ADAU1761_REC_MIXER_RIGHT_CTL_0_ADDR		0x0C	//rec mixer right 0
#define ADAU1761_REC_MIXER_RIGHT_CTL_1_ADDR		0x0D	//rec mixer right 1
#define ADAU1761_SERPORT_CTL_0_ADDR				0x15	//serial port control 0
#define ADAU1761_SERPORT_CTL_1_ADDR				0x16	//serial port control 1
#define ADAU1761_ADC_CTL_ADDR					0x19	//ADC control addr
#define ADAU1761_PLAY_MIXER_LEFT_CTL_0_ADDR		0x1C	//play mixer left 0
#define ADAU1761_PLAY_MIXER_RIGHT_CTL_0_ADDR	0x1E	//play mixer right 0
#define ADAU1761_PLAY_MIXER_LEFT_ADDR			0x20	//play L/R mixer left
#define ADAU1761_PLAY_MIXER_RIGHT_ADDR			0x21	//play L/R mixer right
#define ADAU1761_PLAY_LEFT_VOL_CTL_ADDR			0x23	//play HP left vol
#define ADAU1761_PLAY_RIGHT_VOL_CTL_ADDR		0x24	//play HP right vol
#define ADAU1761_LINEOUT_LEFT_VOL_CTL_ADDR		0x25	//line output left vol addr
#define ADAU1761_LINEOUT_RIGHT_VOL_CTL_ADDR		0x26	//line output right vol addr
#define ADAU1761_PLAY_PWR_MGMT_ADDR				0x29	//play power management

#define ADAU1761_DAC_CTL_0_ADDR				0x2A	//DAC control 0
#define ADAU1761_DAC_CTL_1_ADDR				0x2B	//DAC control 1
#define ADAU1761_DAC_CTL_2_ADDR				0x2C	//DAC control 2

#define ADAU1761_SER_IN_ROUTE_CTL_ADDR		0xF2	//serial input route control addr
#define ADAU1761_SER_OUT_ROUTE_CTL_ADDR		0xF3	//serial output route control addr
//----------------------------------------------------------------------------

//----------------------------------------------------------------------------
#define ADAU1761_CLKENABLE_0_ADDR	0xF9	//clock enable 0 address offset
#define ADAU1761_CLKENABLE_1_ADDR	0xFA	//clock enable 1 address offset
//----------------------------------------------------------------------------

#define ADAU1761_VOLUP			0x01
#define ADAU1761_VOLDOWN		0x02
#define ADAU1761_VOLABSOLUTE	0x03

/**************************** Type Definitions *******************************/


/**************************/
/*
//initialization register datas that will be written to chip
u8 adau1761_regval_table[ADAU1761_REG_NUM]=
{
//	value	addr	description

	0X0F,	//0		//use pll clock, input clk frequence = 1024 x fs, core clock enabled
	0x00,	//01	//there is no such register addressed as 0x4001, so clear it.
	
	//=====================================================================
	0X02,	//02	//pll control setting, 0x0271 01dd 1b01.
	0X71,	//03	//Condition: MCLK = 24Mhz, fs = 44.1khz.
	0X01,	//04	//pll output = 45.1584Mhz = 1024 x fs.
	0XDD,	//05	//X = 2, R = 3, M = 625, N = 477
	0X1B,	//06	//refer to table 16 & 17, on page 28 of 93
	0X01,	//07
	//=====================================================================
	
	0X00,	//08	//jack detect, no need, set it to reset value
	0X00,	//09	//Record Power Management, set it to reset value
	
	0X01,	//10/0A	//left line P & N mute, mixer1 enabled
	0X05,	//11/0B	//left diff line in PGA mute, left auxiliary line in 0dB
	0X01,	//12/0C	//right line P & N mute, mixer2 enabled
	0X05,	//13/0D	//right diff line in PGA mute, right auxiliary line in 0dB
	
	0X00,	//14/0E	//left diff input volume control, set to mute and disabled mode.
	0X00,	//15/0F	//right diff input ...........

	//======================================================================
	//registers about micsbias and ALC. Not used, leave them disabled or in default set
	0x00,	//16/10	//micbias set, set micbias disabled.
	0X00,	//17/11
	0X00,	//18/12
	0X00,	//19/13
	0X00,	//20/14
	
	0X00,	//21/15	//serial port control 0, default set
	0X00,	//22/16	//serial port control 1, default set
	0X00,	//23/17	//converter control 0, default set
	0X00,	//24/18	//converter control 1, default set
	0X13,	//25/19	//ADC control, both right and left channel enabled, other set in default set
	
	0X00,	//26/1A	//left volume control, set to 0 as 0dB
	0X00,	//27/1B	//right digital volume control, set to 0 as 0dB
	0X00,	//28/1C	//playback mixer left control reg 0, mute all
	0X00,	//29/1D	//playback mixer left control reg 1, mute all
	0X00,	//30/1E	//playback mixer right control reg 0, mute all
	0X00,	//31/1F	//playback mixer right control reg 1, mute all
	0X00,	//32/20	//
	0X00,	//33/21
	0X00,	//34/22
	0X00,	//35/23
	0X00,	//36/24
	0X00,	//37/25
	0X00,	//38/26
	0X00,	//39/27
	0X00,	//40/28
	0X00,	//41/29
	0X00,	//42/2A
	0X00,	//43/2B
	0X00,	//44/2C
	0X00,	//45/2D	//all iis ports are pulled up
	0X00,	//46/2E		//there is no such register addressed as 2E
	0XAA,	//47/2F
	0X01,	//48/30	//high drive strength
	0X08,	//49/31	//jack detect pin control
	0X00,	//50
	0X00,
	0X00,
	0X00,
	0X00,
	0X00,
	0X00,
	0X00,
	0X00,
	0X00,
	0X00,	//60
	0X00,
	0X00,
	0X00,
	0X00,
	0X00,
	0X00	//66
}; 
*/
/*********************************/

/**************************** Function Definitions *******************************/
void Adau1761_WriteReg(u8 reg_addr_offeset, u8 reg_val);
u8 Adau1761_ReadReg(u8 reg_addr_offeset);
void Adau1761_WriteBytes(u8 reg_addr_offset, u8 *send_buffer, s32 bytecnt);
void Adau1761_ReadBytes(u8 reg_addr_offset, u8 *recv_buffer, s32 bytecnt);
void Adau1761_Init();
XIicPs_IntrHandler Adau1761_IntrHandler();

void Adau1761_PllSet();
void Adau1761_VolSet(u8 volume_dB, u8 volstyle);
void Adau1761_ChannelSet();

/****************************** Macro Functions **********************************/
#define Adau1761_ClkCtl_Set(reg_val)	Adau1761_WriteReg((u8)ADAU1761_CLKCTL_REGADDR,(u8)(reg_val))




#ifdef __cplusplus
}
#endif


#endif

